The present invention relates generally to semiconductor circuits and specifically to input buffer circuits for driving high speed signals.
FIG. 1 shows a typical input buffer circuit 100 for use in High Speed Transceiver Logic (HSTL) applications. Input buffer circuit 100 includes a differential pair formed by NMOS transistors 102 and 104, a current source 106, and a current mirror formed by PMOS transistors 108 and 110. An input signal Vin is provided to the gate of transistor 102, and a reference voltage Vref is provided to the gate of transistor 104. Current source 106 provides a constant bias current Ibias for the differential pair 102 and 104. In response to a voltage differential between Vin and Vref, the differential pair 102 and 104 generates a single-ended output signal at node 112. A well-known buffer 114 coupled to node 112 drives an output waveform Vout in response to the voltage signal at node 112.
The currents I102 and I104 in transistors 102 and 104, respectively, change in response to the differential voltage between Vin and Vref. The sum of currents I102 and I104 always equals Ibias. In addition, the common mode voltage Vcm between transistors 102 and 104 tracks the average of Vin and Vref, i.e., Vcm=(Vin+Vref)/2xe2x88x92VT, where VT, is the threshold voltage for the differential pair. When transistors 102 and 104 are matched, currents I102 and I104 are both equal to Ibias/2 when Vin and Vref are equal. Capacitor 116 models the parasitic capacitance at the common mode voltage VCM node.
When Vin transitions to logic high, i.e., when Vin greater than Vref, transistor 104 turns off and transistor 102 conducts nearly all of Ibias. If transistors 108 and 110 are matched, transistor 110 will mirror the current I102 so that I110=I102. Because transistor 104 is non-conductive, the current I110 charges node 112 toward VDD. In response thereto, buffer 114 transitions Vout to logic high. Conversely, when Vin transitions to logic low, i.e., when Vin less than Vref, transistor 102 turns off and transistor 104 conducts nearly all of Ibias. Because transistor 102 is non-conductive, transistor 110 mirrors a negligible amount of current, i.e., I110≈0. As a result, the current I104 discharges node 112 toward ground potential. In response thereto, buffer 114 transitions Vout to logic low.
Referring also to the illustrative timing diagram of FIG. 2, the rise time of node 112 for low-to-high transitions of Vin is much faster than the fall time of node 112 for high-to-low transitions of Vin For example, when Vin transitions to logic high at time t1, transistor 102 quickly turns on, and the resultant mirrored current I110 quickly charges output node 112 toward VDD. In response thereto, buffer 114 quickly drives Vout to logic high just after time t1. The logic high level of Vin causes the common mode voltage Vcm to increase, albeit more slowly than Vin (because of the parasitic capacitance 116), which in turn causes a decrease in the gate to source voltages Vgs, of transistor 104. Thus, when Vin transitions to logic low at time t2, the Vgs of transistor 104 increases slowly because Vcm is slow to transition. Specifically, as Vin transitions to logic low, transistor 104 does not turn on until Vcm falls at least one threshold voltage below Vref. Because Vcm does not fall as quickly as Vin, there is a delay in transistor 104 turning on to discharge output node 112 toward ground potential, and thus buffer 114 does not drive Vout to logic low until time t3.
The delay (t3xe2x88x92t2) in FIG. 2 driving Vout to logic low undesirably alters the duty cycle of the output waveform Vout, which in turn may lead to downstream logic and/or timing errors. In addition, the delay in driving Vout to logic low may undesirably limit the speed of circuit 100. Note that if the NMOS differential pair 102 and 104 is replaced by a PMOS differential pair, the fall time of Vout will be faster than the rise time Vout, which also undesirably alters the duty cycle of the output waveform Vout. For the circuit 100 of FIG. 1, the duty cycle error may be 10% or more. Therefore, there is a need for an input buffer circuit that is able to effect fast yet balanced output waveform transitions.